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Industry Oriented Courses/Professional from Industries, Government, Research Labs, etc : NS Lab IIT Madras

About

G S Madhusudan

I coordinate the Systems Architecture Research effort in the R.I.S.E group. The program explores CPU arch., secure CPUs/Microkernels, ML/BigData systems, Storage/Interconnect architectures and 5G networks

Processor Design
- Design of RISC-V based processor family - uController, mobile, server, storage processor and HPC variants. Server cores with Differentiated cores for host OS and guest OS 
- SoC interconnects (NoCs for mobile SoCs, multi-stage ring/mesh fabrics for server/HPC)
- Machine learning and Database accelerators
- Non Boolean computing - nano-oscillator based search engines, neuro-morphic and DNA computing elements

Storage/Interconnect
- Unified memory &I/O interconnect based on SRIO/HMC, persistent memory systems.
- Lightstor(TM) - Optical SSD standard using SRIO, NVMe controller. 

Secure/Safety Auto/Aerospace Critical Systems
- Design of Secure CPUs with tagged instructions sets, allied secure/safety critical micro-kernel (EAL 6/ISO26262), formla verification
- Rust based kernels (Oxide)
- Android run-time for L4 MK, Secure tablet/mobile HW 
- Fault Tolerant CPU arch. for Aerospace/Auto safety critical systems
- Autonomous vehicle platform (CPU + sensors + OS )

Data Analytics System Architecture
- Pangea - a unified Machine learning architecture (HW + SW), a complete rethinking of system architecture for machine learning applications, from CPU architecture to the ML stack.
- Performance Engineering of Open Source Biga Data platforms on x86, Power, GPGPUs
- NVRAM/SCM based storage engines, re-architecture of transaction sub-systems

Telecom Systems
- Vector processor based LTE/5G modem (IoT OFDM, 5G mobile handset, Macro base station),
- Open source cognitive radio for universal radio, adaptive mobile networks

HPC Systems
- Power8+/Nvidia P100 based supercomputer building block, optical interconnect and immersion cooling. 180+ 16 bit Teraflops in 2/3U box
- Phase 2 of above system will use Shakti based accelerators as an option


Mr. Shankar Raman completed his BE (Computer Science and Engineering) from Sri Venkateswara College of Engineering, University of Madras. He obtained his M Sc (Engineering) from Indian Institute of Science Bangalore, and Ph. D. from Indian Institute of Technology Madras. He has about 2 and half decades of Industrial experience working for Companies such as Wipro Infotech R&D, HCL HP R&D, and HCL Cisco Offshore Development Centre. Shankar Raman has successfully created two startup companies: one in the area of consulting, and the other in the area of Network Storage product development. He is currently with RISE Lab in the Department of Computer Science and Engineering, IIT Madras. He has published about 20 research papers in the areas of VLSI Design, Computer Architecture, Networking, Software Testing, Internet Power Consumption, and holds a well cited patent in the area of Network Security.
 
Mr. V. S. Vasan holds an undergraduate and masters degree from BITS Pilani and have been working in the IT Industry for close to 25 years now. Vasan has been working with different leading IT companies in many capacities both in India and abroad in the areas of network management, network appliance development and security domains. He has been working close to 7 years with Cisco Systems and have been part of the engineering of different Cisco products.  He has also been involved with engineering a network storage appliance product for a start up company. Currently, Vasan is acting as a senior technical consultant for different organizations and institutions like Secure engineering group in the Computer Science department of IIT (Chennai) in designing and developing indigenous technology solutions in the areas of network and security under the ‘Make in India’ initiative. As part of professional career, Vasan has also been associated in delivering training programs in the areas of Operating System, Computer Networks, Programming Languages, Network Security and Storage Networking to top IT service companies in India as well as premier educational universities.
 
K.S.Venkataraghavan, comes with a rich versatiile background in System design. Venkat finished his B.E(Chem) from Annamalai University Chidhamabarm Tamilnadu India in 1994. He has been associated with IIT Madras for the past 9+ years as a Project Consultant. Venkat has been incharge of both sponsored research projects and product development at RISE LAB, CSE department, IIT Madras. His key contribution has been in the areas of formal verification of safety critical designs;  design, development and deployment of WSN for Civil engineering Structures. Prior to joining RISE Lab CSE Department at IIT, Venkat  was associated with Brovis wireless networks, Midas Communication, TENET Group , Electrical Sciences department-IIT Madras and Real Chip Communications and T.E.A.M. At Midas communications and TENET Group , he was in charge of design development and engineering management of Cable-Wirless customer premisies equipment System  design. At Real Chip communications,the first Fabless Seminconductor design company, he was a key member both in SOC design and Verification. He was incharge of managing variety of EDA tool licenses and large and complex SOC design database across continents. Venkat is incharge of the Low Power Wireless Embedded Design vertical which finds wide range of applications in WSN ,IOT and networking hardware domain. His area of expertise include SOC verification,Embedded system design and Product engineering management.
 
 
Mr. Sudhakar M, has 15 years of experience in Enterprise IT Infrastructure Services. Currently he is working as Technical Consultant in TATA Consultancy Services (TCS) and is responsible for design, and implementation of - Enterprise Data Centers Services, Data Networking and Infrastructure Server.  Services for various Banking and Financial Services clients. He played various technical roles in TCS including Network Engineer, Technical Lead, Portfolio manager, Data Center Manger and Solution Architect.He has completed A.M.I.E (CSE) from “The Institution of Engineers (India)” and M.Tech (CSE) from SRM University. Currently he is pursuing PhD (Part-Time) from IIT-Madras and his research interest is on next generation secured network architecture.
 
 
Sarath Kumar Kandalam completed his B.Tech.(Electronics and Communication Engineering) from Sri Venkateswara University College of Engineering, Tirupati. He completed his M. Tech. (Integrated Electronic Circuits) from Indian Institute of Technology, New Delhi. He has about 9 years of industry experience in companies like Intel and Bharat electronics. Sarath is working for Intel on graphics core development for six years. He is currently associated with RISE Lab in Department of Computer Science and Engineering, IIT Madras. He has been involved in designing of file systems, kernel changes related to new non-volatile memory storage systems. He has proficiency in scripting languages such as bash, tcsh, perl and hardware description languages like VHDL and system verilog.

Details

Subject :
Information Security
Start :
06-Jul-2015
End :
06-Jul-2015
Venue :
NS Lab IIT Madras
Registration Status :
0

Workshop / Event co-ordinator Detail

Name :
Prof V. Kamakoti
Mobile :
9790968632
Email :
veezhi@gmail.com

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